High-performance on-chip inductors are increasingly needed for a wide range of environments, such as wireless communication systems and micro-electromechanical systems (MEMS). Planar coil inductors with moderate quality factor (Q) can be integrated with other radio frequency (RF) circuits by using standard integrated circuit (IC) fabrication processes. The effectiveness of these on-chip inductors in RF systems and other environments depends upon, among other parameters, loss, and parasitics due to the substrate on which the inductor is formed.
Typically, planar coil inductors are directly fabricated onto a dielectric layer on top of an electrically-lossy semiconductor substrate, such as silicon. This lowers the quality factor and degrades the performance of planar coil inductors by introducing extra loss, noise, and parasitic capacitance. In addition, the conventional planar coil inductor requires a significant footprint to achieve a required inductance. This reduces the overall density of integration and increases the cost of finished devices, as the semiconductor substrates are expensive.
Recently, fabrication techniques have been employed to reduce the adverse influence of the substrate, such as using a high resistivity substrate, coating organic dielectric materials such as polyimide to increase thickness of the dielectric layer underneath the inductor, and/or partially or completely removing the substrate underneath the inductor. More recently, surface micromachining technology has been applied in the fabrication of planar coil inductors to create an air gap between the inductor and the substrate. However, all of these procedures require additional fabrication steps, and many of these steps may not be compatible with standard IC fabrication processes. In other words, the chances for such processes to be accepted by standard IC foundry are minimal. Furthermore, none of these conventional methods addresses the problem of the large footprint of typical planar coil inductors.